The present invention relates to computer systems. More particularly, it relates to the control of data flow between processors of a multiprocessor system.
In the art of digital data processing systems, such systems may include a plurality of individual processing units, each having its own unique cache memory. At the same time, the several processing units may share a common main memory. In the interest of maximizing the throughput of the processing unit, it is known to operate the cache memories on a store-into basis. In other words, for data that has been extracted from the main memory and operated uponor modified by one of the processing units, the resulting data is stored only in the cache memory associated with that processing unit. Under those conditions, the only location of the latest version of modified data is in the cache associated with that processing unit. The same data block remaining in the main memory will be invalid. If, now, one of the other processors has a need for the same block of data, means must be provided for making the latest form of the data available to the requesting processor.
The problem has been addressed in an earlier patent, U.S. Pat. No. 3,735,360--Anderson, et al. In that patent there is disclosed a system wherein a record is kept in each of the cache memory units indicative that the only valid copy of the required data is located in one of the cache memories. Thus, on demand the required data is transferred from the cache where it is found back to the main memory and then accessed from the main memory to the requesting processing unit. Such a system is, of necessity, slow in that the main-memory, a much slower unit must be accessed twice for each such transfer.